高級(jí)模擬IC開發(fā)工程師
工作地：深圳????崗位數(shù)量：4
崗位職責(zé)：
1． 參與模擬或數(shù)模混合的電源IC產(chǎn)品研發(fā)，能獨(dú)立完成系統(tǒng)方案、可行性分析、規(guī)格定義。
2． 可帶領(lǐng)團(tuán)隊(duì)一起完成電源IC的設(shè)計(jì)任務(wù),能指導(dǎo)版圖工程師的工作。
3． 可獨(dú)立負(fù)責(zé)分析和設(shè)計(jì)電路。
4． 可獨(dú)立負(fù)責(zé)模塊及整體芯片的版圖布局設(shè)計(jì)。
5． 參與datasheet及application?note等技術(shù)文檔的撰寫。
6． 參與流片、封裝、測(cè)試等相關(guān)工作。
崗位要求：
1． 要求有DC-DC設(shè)計(jì)經(jīng)驗(yàn)，能熟練分析和設(shè)計(jì)環(huán)路補(bǔ)償；
2． 要求能熟練設(shè)計(jì)運(yùn)放和高速比較器等基本模塊；
3． 要求熟悉DC-DC?IC可靠性設(shè)計(jì)，掌握寄生、噪聲產(chǎn)生原理和解決方案；
4． 了解模擬版圖布局方法，熟悉高壓CMOS和BCD工藝者優(yōu)先；
5． 有高壓大電流DC-DC設(shè)計(jì)經(jīng)驗(yàn)者優(yōu)先，有MHz以上開關(guān)頻率設(shè)計(jì)經(jīng)驗(yàn)者尤佳；
6． 熟練使用Cadence等電路設(shè)計(jì)軟件，包括spectre，hsipce，veriloga,virtuoso,layout?tools等，熟悉AMS或layout?XL者優(yōu)先；
7． 熟悉各類實(shí)驗(yàn)室測(cè)試設(shè)備、有debug、失效分析經(jīng)驗(yàn)者優(yōu)先；
8． 有高精度儀表、運(yùn)放使用經(jīng)驗(yàn)者優(yōu)先。
9． 有低功耗、低成本設(shè)計(jì)和高功率設(shè)計(jì)經(jīng)驗(yàn)者優(yōu)先。
10． 良好的溝通，工作態(tài)度主動(dòng)積極。
11． 碩士及以上學(xué)歷，微電子/電力電子相關(guān)專業(yè)畢業(yè)，5年及以上工作經(jīng)驗(yàn)。
Senior?Analog?IC?designer
working?location：ShenZhen????????position?count?：4
job?duties：
1. Designing?ICs?for?analog?and?mixed-signal?power?management,?including?feasibility?and?cost?study?and?defining?or?following?a?specification.
2. Leading?a?design?team?to?design?power?management?ICs,?and?supervising?the?layout?team.
3. Responsible?for?analysis?and?design?at?the?circuit?level.
4. Responsible?for?the?floorplan?along?with?ESD?and?any?other?circuitry?required?for?a?production?worthy?chip.
5. Writing?or?supervising?writing?of?datasheets?and?application?notes
6. Monitoring?and?advising?of?the?backend?flow?from?design?to?production?including?tapeout,?packaging,?PCB?board?design?and?layout,?automatic?testing?(ATE),?characterization,?ESD?testing,?and?reliability.
Job?requirements:
1． Experience?with?DC/DC?converters?is?required.
2． Experience?with?the?basic?analog?building?blocks?including?different?amplifiers?and?high-speeed?comparators?is?required.
3． Well?known?about?reliability?design?with?DC-DC?IC,?well?known?about?the?parasitic?channel?or?noise?principle?and?solve?method?with?DC-DC?IC.
4． Experience?with?analog?layout?techniques,?and?knowledge?of?high?voltage?CMOS?and?BCD?processes.
5． High?voltage?with?high?current?DC/DC?is?preferred,?MHz?switch?frequency?is?a?plus.
6． Skillful?usage?of?Cadence?software,?Spectre,?Hspice,virtuoso,?verilogA,?layout?tools?etc.??Experience?with?AMS?and?layout?XL?is?preferred.
7． Experience?in?the?lab?and?familiarity?with?different?test?equipments?along?with?characterization,?identification?of?bugs,?debug?and?external?fixes?required.
8． Experience?with?precision?and/or?instrumentation?amplifiers?and?ADC?is?preferred.
9． Ultra?low?power?and?high?power?experience?or?cost?saving?techniques?is?preferred.
10． Good?communication?skills?and?a?positive?working?attitude.
11． Masters?degree?and?above?with?a?focus?on?microelectronics?or?power?electronics?and?5?years?working?experience?at?least.