Job?Description:Participate?in?architecture?and?design?verification?of?complex?networking?ASIC.??Responsibilities?include:-????????Standalone?and?Integrated?functional?verification;-????????Documentation?and?review?of?Verification?architecture?and?testplans-????????Develop?verification?environment?(models,?checkers,?packet?manager)?using?SystemVerilog-????????Develop?random,?pseudo-random?and?directed?tests-????????Establish?verification?effectiveness?using?assertion/functional/code?coverage?and?code?reviews-????????RTL?and?gates?simulation,?debug?and?root?cause-????????Regression?triage?and?debug-????????Formal?verification?and?equivalence?checking.-????????Lab?debug?and?design?validationSkills?required:-????????Prior?significant?verification?experience?on?complex?ASICs.-????????Knowledge?of?SSD?is?a?plus-????????Outstanding?coding?and?scripting?skills?(Verilog,?C,?Perl).?SystemVerilog?is?a?plus.-????????Chip?and?system?and?test?experience.-????????Good?planning?skills?(well?partitioned?designs,?well?organized?code)-????????Outstanding?written?and?verbal?communication?skills-????????Capability?of?critical?thinking,?challenging?design?intent-????????Master?degree?is?preferred.-????????At?least?2?years?work?experiences?.