Job?Responsibilities:
1.?????Develop?reference?designs?on?FPGA-based??prototyping?systems;
2.?????Perform?customer?service?projects;
3.?????New?products?survey?and?research;
4.?????Develop?Application?Notes.
Job?Requirements:
1.?????At?least?five?years?of?RTL?design?experiences.??Familiarity?with?Verilog?or?VHDL?and?FPGA?simulation?tools;
2.?????Deep?background?on?FPGA?Prototype?partition,??familiar?with?commercial?FPGA?partition?tools?as?well?as?manually?partitioning??a?complex?multiple-FPGA?design;
3.?????Deep?background?on?using?Xilinx?or?Altera?FPGA,??ASIC?to?FPGA?design?memory?modeling,?tune?FPGA?timing?constraint;
4.?????Experience?in?SoC?design?is?a?plus;
5.?????Experience?in?developing?or?using?digital?or??analog?commercial?IP?is?a?plus;
6.?????Experience?in?C,?C++,?or?SystemC?is?a?plus;
7.?????Experience?in?Perl?or?TCL?is?a?plus;
8.?????Good?English?language?skills?(reading/writing??skills?essential,?oral?skills?highly?desirable);
9.?????Some?business?travels?(international?or?domestic)?.
職位職責(zé)：
1.?????開發(fā)基于FPGA原型系統(tǒng)的參考設(shè)計(jì)；
2.?????執(zhí)行客戶服務(wù)項(xiàng)目；
3.?????新產(chǎn)品調(diào)研；
4.?????產(chǎn)品應(yīng)用范例開發(fā)。
職位要求：
1.?????至少5年以上的RTL設(shè)計(jì)經(jīng)驗(yàn)。熟練掌握Verilog,VHDL以及仿真工具的使用；
2.?????深入了解FPGA原型設(shè)計(jì)分割技術(shù)，熟悉商業(yè)FPGA分割工具的使用，同時(shí)也有手動(dòng)分割復(fù)雜SOC設(shè)計(jì)到多顆FPGA的經(jīng)驗(yàn)；
3.?????深入了解Altera或Xilinx?FPGA的使用，具有將ASIC設(shè)計(jì)轉(zhuǎn)到FPGA設(shè)計(jì)的Memory?Modeling,?時(shí)序調(diào)整和優(yōu)化的板級調(diào)試經(jīng)驗(yàn)；
4.?????有SoC設(shè)計(jì)經(jīng)驗(yàn)者優(yōu)先；
5.?????有數(shù)字或模擬IP的開發(fā)或使用經(jīng)驗(yàn)者優(yōu)先；
6.?????有C,??C++或SystemC的使用經(jīng)驗(yàn)者優(yōu)先；
7.?????有Perl或TCL的使用經(jīng)驗(yàn)者優(yōu)先；
8.?????具有良好的英語水平（讀，寫熟練以及口語流利）；
9.?????能夠進(jìn)行商務(wù)旅行（國際或國內(nèi)）。